00C0-00DF ---- DMA 2   (second Direct Memory Access controller 8237)


00C0   r/w DMA channel 4 memory address bytes 1 and 0 (low) (ISA, EISA)
00C2   r/w DMA channel 4 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C4   r/w DMA channel 5 memory address bytes 1 and 0 (low) (ISA, EISA)
00C6   r/w DMA channel 5 transfer count bytes 1 and 0 (low) (ISA, EISA)
00C8   r/w DMA channel 6 memory address bytes 1 and 0 (low) (ISA, EISA)
00CA   r/w DMA channel 6 transfer count bytes 1 and 0 (low) (ISA, EISA)
00CC   r/w DMA channel 7 memory address byte 0 (low), then 1 (ISA, EISA)
00CE   r/w DMA channel 7 transfer count byte 0 (low), then 1 (ISA, EISA)

00D0   r   DMA channel 4-7 status register (ISA, EISA)
        bit 7 = 1  channel 7 request
        bit 6 = 1  channel 6 request
        bit 5 = 1  channel 5 request
        bit 4 = 1  channel 4 request
        bit 3 = 1  terminal count on channel 7
        bit 2 = 1  terminal count on channel 6
        bit 1 = 1  terminal count on channel 5
        bit 0 = 1  terminal count on channel 4

00D0   w   DMA channel 4-7 command register (ISA, EISA)
        bit 7 = 1  DACK sense active high
              = 0  DACK sense active low
        bit 6 = 1  DREQ sense active high
              = 0  DREQ sense active low
        bit 5 = 1  extended write selection
              = 0  late write selection
        bit 4 = 1  rotating priority
              = 0  fixed priority
        bit 3 = 1  compressed timing
              = 0  normal timing
        bit 2 = 0  enable controller
        bit 1 = 1  enable memory-to-memory transfer
        bit 0      .....

00D2   w   DMA channel 4-7 write request register (ISA, EISA)

00D4   w   DMA channel 4-7 write single mask register (ISA, EISA)
        bit 7-3      reserved
        bit 2   = 0  clear mask bit
            = 1  set mask bit
        bit 1-0 = 00 channel 4 select
            = 01 channel 5 select
            = 10 channel 6 select
            = 11 channel 7 select

00D6   w   DMA channel 4-7 mode register (ISA, EISA)
        bit 7-6 = 00  demand mode
            = 01  single mode
            = 10  block mode
            = 11  cascade mode
        bit 5   = 0   address increment select
            = 1   address decrement select
        bit 4   = 0   autoinitialisation disable
            = 1   autoinitialisation enable
        bit 3-2 = 00  verify operation
            = 01  write to memory
            = 10  read from memory
            = 11  reserved
        bit 1-0 = 00  channel 4 select
            = 01  channel 5 select
            = 10  channel 6 select
            = 11  channel 7 select

00D8   w   DMA channel 4-7 clear byte pointer flip-flop (ISA, EISA)
00DA   r   DMA channel 4-7 read temporary register (ISA, EISA)
00DA   w   DMA channel 4-7 master clear (ISA, EISA)
00DC   w   DMA channel 4-7 clear mask register (ISA, EISA)
00DE   w   DMA channel 4-7 write mask register (ISA, EISA)

00E0       split address register, memory encoding registers PS/2m80 only